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LTC4558 1 4558f typical application features applications description dual sim/smart card power supply and interface the ltc ? 4558 provides the power conversion and signal level translation needed for advanced cellular telephones to interface with 1.8v or 3v subscriber identity modules (sims). the device meets all requirements for 1.8v and 3v sims and contains ldo regulators to power 1.8v or 3v sim cards from a 2.7v to 5.5v input. the output voltages can be set using the two voltage selection pins and up to 50ma of load current can be supplied. a channel select pin determines which channel is open for communication. separate enable pins for each channel allow both cards to be powered at once and allow for faster transition from one channel to the other. internal level translators allow controllers operating with supplies as low as 1.4v to interface with 1.8v or 3v smart cards. battery life is maximized by a low operating cur- rent of 65a and a shutdown current of less than 1a. board area is minimized by the low pro? le 3mm 3mm 0.75mm leadless qfn package. deactivation sequence power management and control for two sim cards or smart cards independent 1.8v/3v v cc control for both cards supports simultaneous powering of both cards fast channel switching automatic level translation dynamic pull-ups deliver fast signal rise times* built-in fault protection circuitry automatic activation/deactivation sequencing circuitry low operating/shutdown current > 10kv esd on sim card pins meets emv fault tolerance requirements low pro? le 20-lead (3mm 3mm) qfn package gsm, td-scdma and other 3g + cellular phones wireless point-of-sale terminals multiple sim card interfaces , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. *protected by u.s. patents, including 6356140. dv cc v batt v batt 3v to 6v dv cc 1.4v to 4.4v LTC4558 controller v cca i/oa dv cc rsta clka c1 c1 c5 c5 c3 c2 c7 c7 c2 c3 gnd v ccb clkb rstb i/ob clkin 0.1 f 1 f 1 f rstin data csel vsela vselb enablea enableb clkruna clkrunb 0.1 f 4558 ta01 1.8v/3v sim card a 1.8v/3v sim card b v cc i/o rst clk gnd gnd v cc clk rst i/o rstx 5v/div clkx 5v/div i/ox 5v/div v ccx 2v/div 10 s/div c vccx = 1 f 4558 ta02
LTC4558 2 4558f package/order information electrical characteristics absolute maximum ratings v batt , dv cc , data, rstin, clkin, clkruna, clkrunb, enablea, enableb, csel, vsela, vselb to gnd ............................................. C 0.3v to 6v i/oa, clka, rsta ........................ C 0.3v to vcca + 0.3v i/ob, clkb, rstb ........................ C 0.3v to vccb + 0.3v i cca,b (note 4) .......................................................80ma v cca,b short-circuit duration ........................... inde? nite operating temperature range (note 3) ...C40c to 85c storage temperature range ...................C65c to 125c (note 1) parameter conditions min typ max units input power supply v batt operating voltage 2.7 5.5 v i vbatt operating current v cca = 3v, v ccb = 0v, i cca = 0a v cca = 1.8v, v ccb = 0v, i cca = i ccb = 0a 65 65 100 100 a a dv cc operating voltage 1.4 5.5 v i dvcc operating current 610 a i dvcc shutdown current 0.1 1 a i vbatt shutdown current dv cc = 0v 0.1 1 a sim card supplies v cca,b output voltage 3v mode, 0ma < i cca,b < 50ma 1.8v mode, 0ma < i cca,b < 30ma 2.85 1.71 3.00 1.8 3.15 1.89 v v v cca,b turn-on time i cca,b = 0ma, enablea,b to v cca,b at 90% selected voltage 0.8 1.5 ms channel switching time enablea = enableb = rstin = dv cc csel to rstb 1s 20 19 18 17 16 7 8 top view 21 ud package 20-lead (3mm 3mm) plastic qfn 9 10 v ccb dv cc v batt v cca clka clkrunb clkruna csel vsela enablea clkb rstb i/ob enableb vselb rsta i/oa data rstin clkin 12 11 13 14 15 4 5 3 2 1 6 t jmax = 125c, ja = 68c/w, jc = 4.2c/w exposed pad (pin 21) is gnd, must be soldered to pcb order part number ud part marking LTC4558eud lcsh order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v batt = 3.3v, dv cc = 1.8v, c a = c b = 1f, unless otherwise speci? ed.
LTC4558 3 4558f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: this speci? cation applies to both smart card classes. parameter conditions min typ max units clka,b low level output voltage (v ol ) sink current = C 200a (note 2) 0.2 v high level output voltage (v oh ) source current = 200a (note 2) v cca,b C0.2 v rise/fall time loaded with 50pf (10% to 90%) (note 2) 16 ns clka,b frequency (note 2) 10 mhz rsta,b low level output voltage (v ol ) sink current = C 200a (note 2) 0.2 v high level output voltage (v oh ) source current = 200a (note 2) v cca,b C0.2 v rise/fall time loaded with 50pf (10% to 90%) (note 2) 100 ns i/oa, i/ob low level output voltage (v ol ) sink current = C 1ma (v data = 0v) (note 2) 0.3 v high level output voltage (v oh ) source current = 20a (v data = v dvcc ) (note 2) 0.85 ? v cca,b v rise/fall time loaded with 50pf (10% to 90%) (note 2) 500 ns short-circuit current v data = 0v (note 2) 510 ma data low level output voltage (v ol ) sink current = C 500a (v i/oa,b = 0v) 0.3 v high level output voltage (v oh ) source current = 20a (v i/oa,b = v cca,b ) 0.8 ? dv cc v rise/fall time loaded with 50pf (10% to 90%) 125 500 ns enablea, enableb, rstin, clkin, csel, vsela, vselb, clkruna, clkrunb low input threshold (v il ) 0.15 ? dv cc v high input threshold (v ih ) 0.85 ? dv cc v input current (i ih /i il ) C1 1 a electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v batt = 3.3v, dv cc = 1.8v, c a = c b = 1f, unless otherwise speci? ed. note 3: the LTC4558e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 4: based on long-term current density limitations.
LTC4558 4 4558f v batt supply voltage (v) 2.7 3.1 50 v batt supply current ( a) 70 65 80 75 100 3.5 4.3 4.7 4557 g01 60 55 95 90 85 3.9 5.1 5.5 t a = 25 c i cca = i ccb = 0 a v ccx = 3v v ccx = 1.8v dropout temperature ( c) ?0 short-circuit current (ma) 6.0 5.5 5.0 6.5 60 4557 g02 4.5 4.0 ?5 10 35 85 7.0 v dvcc = v batt = 5.5v v ccx = 3v i/ox shorted to v ccx load current ( a) 100 v batt quiescent current ( a) 150 250 10 1000 10000 100000 4557 g03 0 100 200 50 t a = 25 c v batt = 3.1v v batt supply voltage (v) 2.7 v batt shutdown current ( a) 2.0 2.5 3.0 3.5 4.0 3.9 4.7 4557 g04 1.5 1.0 3.1 3.5 4.3 5.1 5.5 0.5 0 v dvcc = 1.8v t a = 40 c t a = 85 c t a = 25 c dv cc supply voltage (v) 1.2 0 dv cc shutdown current ( a) 0.1 0.3 0.4 0.5 1.6 3.2 4.0 4557 g05 0.2 0.6 2.8 4.8 5.6 5.2 2.0 2.4 3.6 4.4 v batt = 5.5v t a = ?0 c to 85 c typical performance characteristics no load supply current vs v batt i/ox short-circuit current vs temperature v batt quiescent current (i vbatt C i cc ) vs load current v batt shutdown current vs supply voltage dv cc shutdown current vs supply voltage t a = 25c unless otherwise noted.
LTC4558 5 4558f i/0x 1v/div data 1v/div 200ns/div 4557 g06 rstx 5v/div clkx 5v/div i/ox 5v/div v ccx 2v/div 20 s/div 4557 g07 typical performance characteristics data C i/o channel, c l = 40pf deactivation sequence, c vccx = 1f t a = 25c unless otherwise noted.
LTC4558 6 4558f pin functions dv cc (pin 2): power. reference voltage for the control logic. v batt (pin 3): power. supply voltage for the analog sec- tions of the LTC4558. v cca ,v ccb (pins 4, 1): card socket. the v cca ,v ccb pins should be connected to the v cc pins of the respective card sockets. the activation of the v cca ,v ccb pins are controlled by enablea and enableb. they can be set to 1.8v or 3v via the vsela and vselb inputs. clka,cklb (pins 5, 20): card socket. the clka,cklb pins should be connected to the clk pins of the respective card sockets. the clka,cklb signals are derived from the clkin pin. they provide a level shifted clkin signal to the selected card. the clka,cklb pins are gated off until v cca ,v ccb attain their correct values. when a card socket is deselected, its clk pin may be left active or brought low using the clkruna, clkrunb pins. rsta,rstb (pins 6, 19): card socket. the rsta,rstb pins should be connected to the rst pins of the respec- tive card sockets. the rsta,rstb signals are derived from the rstin pin. when a card is selected, its rst pin follows rstin. the rsta,rstb pins are gated off until v cca ,v ccb attain their correct values. when a card socket is deselected, the state of its rst pin is latched to its current state. i/oa,i/ob (pins 7, 18): card socket. the i/oa,i/ob pins should be connected to the i/o pins of the respective card sockets. when a card is selected, its i/o pin transmits/re- ceives data to/from the data pin. the i/oa,i/ob pins are gated off until v cca ,v ccb attain their correct values. data (pin 8): input/output. microcontroller side data i/o pin. the data pin provides the bidirectional communication path to both cards. one of the cards may be selected to communicate via the data pin at a time. the pin possesses a weak pull-up current source, allowing the controller to use an open drain output and maintain a high state during shutdown, as long as dv cc is powered. rstin (pin 9): input. the rstin pin supplies the reset signal to the cards. it is level shifted and transmitted directly to the rst pin of the selected card. clkin (pin 10): input. the clkin pin supplies the clock signal to the cards. it is level shifted and transmitted di- rectly to the clk pin of the selected card. if clkruna,b is high, the clock signal will be transmitted to the clka,b pin, regardless of whether that card is selected, as long as that card socket is enabled. enablea, enableb (pins 11, 17): inputs. the enablea and enableb pins enable or disable channel a and chan- nel b, respectively. vsela, vselb (pins 12, 16): inputs. the vsela and vselb pins select the voltage level of each set of sim/ smart card pins. bringing either of these pins high will set the output level of its respective channel to 3v. bring- ing either of these pins low will set the output level of its respective channel to 1.8v. csel (pin 13): input. the csel pin selects which set of sim/smart card pins are active. clkruna, clkrunb (pins 14, 15): inputs. the clkruna and clkrunb inputs are used to select whether the clock signal is always sent to card sockets that are enabled or whether the clock is gated with the csel pin. exposed pad (pin 21): ground. this ground pad must be soldered directly to a pcb ground plane.
LTC4558 7 4558f block diagram 7 4 i/oa v cca 1 v ccb 18 i/ob 19 rstb 20 17 16 11 21 clkb 6 rsta 5 clka 14 clkruna 8 data 9 rstin 10 clkin ldoa ldob v batt dv cc dv cc 3 dv cc 2 control logic 4558 bd 12 vsela enablea vselb enableb 13 csel gnd 15 clkrunb
LTC4558 8 4558f operation the LTC4558 features two independent sim/smart card channels. only one of these channels may be open for communication at a time however both channels can be enabled and made ready for communication using the enablea and enableb pins. this allows faster transi- tion from one channel to the other. each channel is able to produce two voltage levels, 1.8v and 3v. the channel selection and voltage selection are controlled by the csel, vsela and vselb pins as shown in the table below: bidirectional channels the bidirectional channels are level shifted to the appro- priate v cca,b voltages at the i/oa,b pins. an nmos pass transistor performs the level shifting. the gate of the nmos transistor is biased such that the transistor is completely off when both sides have relinquished the channel. if one side of the channel asserts a low, then the transistor will convey the low to the other side. note that current passes from the receiving side of the channel to the transmitting side. the low output voltage of the receiving side will be dependent upon the voltage at the transmitting side plus the ir drop of the pass transistor. when a card socket is selected, it becomes a candidate to drive data on the data pin and likewise receive data from the data pin. when a card socket is deselected, its i/o pin will be pulled high and communication with the data pin will be disabled. if both channels are disabled, a weak pull-up ensures that the data pin is held high, as long as dv cc is powered. dynamic pull-up current sources the current sources on the bidirectional pins (data,i/oa,b) are dynamically activated to achieve a fast rise time with a relatively small static current. once a bidirectional pin is relinquished, a small start-up current begins to charge the node. an edge rate detector determines if the pin is released by comparing its slew rate with an internal refer- ence value. if a valid transition is detected, a large pull-up current enhances the edge rate on the node. the higher slew rate corroborates the decision to charge the node thereby affecting a dynamic form of hysteresis. reset channels when a card is selected, the reset channel provides a level shifted path from the rstin pin to the rst pin of the selected card. when a card is deselected, the last state of the rsta,b pin is latched. this allows a deselected card to remain active, and therefore eliminates delays associated with card initialization. clock run mode various sim/smart cards may have different requirements for the state of the clock pin when the channel is not open for communication. the clkruna,b pins allow the user to select whether the clock is brought low after the channel is deselected or allowed to run. if a channel is enabled, bringing its clkrun pin high will transmit the clock to the corresponding card socket, whether or not the channel is selected using the csel. figure 1. dynamic pull-up current source table 1. channel and voltage truth table csel vsela vselb selected card voltages a b 0 0 0 a 1.8v 1.8v 0 0 1 a 1.8v 3v 0 1 0 a 3v 1.8v 011 a 3v3v 1 0 0 b 1.8v 1.8v 1 0 1 b 1.8v 3v 1 1 0 b 3v 1.8v 111 b 3v3v v ref 4558 f01 i start bidirectional pin local supply dv dt +
LTC4558 9 4558f activation/deactivation activation and deactivation sequencing is handled by built- in circuitry. each channel may be activated or deactivated independently of the other. the activation sequence for each channel is initiated by bringing the enablea,b pin high. the activation sequence is outlined below: 1. the rsta,b, clka,b and i/oa,b pins are held low. 2. v cca,b is enabled. 3. after v cca,b is stable at its selected level, the i/oa,b and rsta,b channels are enabled. 4. the clock channel is enabled on the rising edge of the second clock cycle after the i/oa,b pin is enabled. the deactivation sequence is initiated by bringing the enablea,b pin low. the deactivation sequence is out- lined below: 1. the reset channel is disabled and rsta,b is brought low. 2. the clock channel is disabled and the clka,b pin is brought low two clock cycles after enablea,b is brought low. if the clock is not running, the clock channel will be disabled approximately 9s after the enablea,b pin is brought low. 3. the i/o channel is disabled and the i/oa,b pin is brought low approximately 9s after the enablea,b pin is brought low. 4. v cca,b will be depowered after the i/oa,b pin is brought low. the activation or deactivation sequences will take place every time a card channel is enabled or disabled. when a channel is deselected using the csel pin, the rsta,b state is latched, the i/oa,b channel becomes high imped- ance and clka,b is brought low after a maximum of two clock cycles. fault detection the v cca,b , i/oa,b, rsta,b, clka,b and data pins are all protected against short-circuit faults. while there are no logic outputs to indicate that a fault has occurred, these pins will be able to tolerate the fault condition until it has been removed. the v cca,b , i/oa,b, and rsta,b pins possess fault protec- tion circuitry which will limit the current available to the pins. each v cc pin is capable of supplying approximately 90ma (typ) before the output voltage is reduced. the clka,b pins are designed to tolerate faults by reducing the current drive capability of their output stages. after a fault is detected by the internal fault detection logic, the logic waits for a fault detection delay to elapse before reducing the current drive capability of the output stage. the reduced current drive allows the LTC4558 to detect when the fault has been removed. operation
LTC4558 10 4558f 10kv esd protection all smart card pins (clka,b, rsta,b, i/oa,b, v cca,b and gnd) can withstand over 10kv of human body model esd in-situ. in order to ensure proper esd protection, careful board layout is required. the gnd pin should be tied di- rectly to a ground plane. the v cca,b capacitors should be located very close to the v cca,b pins and tied immediately to the ground plane. capacitor selection a total of four capacitors is required to operate the LTC4558. an input bypass capacitor is required at v batt and dv cc . output bypass capacitors are required on each of the smart card v cc pins. there are several types of ceramic capacitors available, each having considerably different characteristics. for example, x7r ceramic capacitors have excellent voltage and temperature stability but relatively low packing density. y5v and x5r ceramic capacitors have apparently higher applications information figure 2. additional components for improved compliance testing packing density but poor performance over their rated voltage or temperature ranges. under certain voltage and temperature conditions y5v, x5r and x7r ceramic capacitors can be compared directly by case size rather than speci? ed value for a desired minimum capacitance. the v cca,b outputs should be bypassed to gnd with a 1f capacitor. a low esr ceramic capacitor is recommended on each v cc pin to ensure esd compliance. v batt and dv cc should be bypassed with 0.1f ceramic capacitors. compliance testing inductance due to long leads on type approval equipment can cause ringing and overshoot that leads to testing prob- lems. small amounts of capacitance and damping resistors can be included in the application without compromising the normal electrical performance of the LTC4558 or smart card system. generally a 100 resistor and a 20pf capaci- tor will accomplish this, as shown in figure 2. 100 ? 100 ? 100 ? 20pf 20pf 20pf 20pf 1 f 4558 f02 v cca,b clka,b LTC4558 rsta,b i/oa,b smart card socket
LTC4558 11 4558f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?xposed pad 1.65 0.10 (4-sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 0.20 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 19 20 2 0.40 bsc 0.200 ref 2.10 0.05 3.50 0.05 (4 sides) 0.70 0.05 0.00 ?0.05 (ud20) qfn 0306 rev a 0.20 0.05 0.40 bsc package outline ud package 20-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1720 rev a)
LTC4558 12 4558f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2007 lt 0107 ? printed in usa part number description comments ltc1555l/ ltc1555l-1.8 1mhz, sim power supply and level translator for 1.8v/3v/5v sim cards v in : 2.6v to 6.6v, v out = 1.8v/3v/5v, i q = 32a, i sd < 1a, ssop16 ltc1555/ltc1556 650khz, sim power supply and level translator for 3v/5v sim cards v in : 2.7v to 10v, v out = 3v/5v, i q = 60a, i sd < 1a, ssop16, ssop20 ltc1755/ltc1756 850khz, smart card interface with serial control for 3v/5v smart card applications v in : 2.7v to 7v, v out = 3v/5v, i q = 60a, i sd < 1a, ssop16, ssop24 ltc1955 dual smart card interface with serial control for 1.8v/3v/5v smart card applications v in : 3v to 5.5v, v out = 1.8v/3v/5v, i q = 200a, i sd < 1a, qfn32 ltc1986 900khz, sim power supply for 3v/5v sim cards v in : 2.6v to 4.4v, v out = 3v/5v, i q = 14a, i sd < 1a, thinsot ltc4555 sim power supply and level translator for 1.8v/3v sim cards v in : 3v to 6v, v out = 1.8v/3v, i q = 40a, i sd < 1a, qfn16 ltc4556 smart card interface with serial control v in : 2.7v to 5.5v, v out = 1.8v/3v/5v, i q = 250a, i sd < 1a, 4 4 qfn24 ltc4557 dual sim/smart card power supply and level translator for 1.8v/3v cards v in : 2.7v to 5.5v, v out = 1.8v/3v, i q = 250a, i sd < 1a, qfn16 thinsot is a trademark of linear technology corporation. related parts typical application dv cc v batt v batt 3v to 6v dv cc 1.4v to 4.4v LTC4558 controller v cca i/oa dv cc rsta clka c1 c1 c5 c5 c3 c2 c7 c7 c2 c3 gnd v ccb clkb rstb i/ob clkin c4 0.1 f c1 1 f c2 1 f rstin data csel vsela vselb enablea enableb clkruna clkrunb c3 0.1 f 4558 ta01a 1.8v/3v sim card a 1.8v/3v sim card b v cc i/o rst clk gnd gnd v cc clk rst i/o

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